Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date         : Sun Apr 12 14:22:42 2026
| Host         : debian running 64-bit Debian GNU/Linux 13 (trixie)
| Command      : report_timing_summary -max_paths 10 -report_unconstrained -warn_on_violation -file system_wrapper_timing_summary_postroute_physopted.rpt -pb system_wrapper_timing_summary_postroute_physopted.pb -rpx system_wrapper_timing_summary_postroute_physopted.rpx
| Design       : system_wrapper
| Device       : 7z020-clg400
| Speed File   : -1  PRODUCTION 1.12 2019-11-22
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule       Severity  Description                                      Violations  
---------  --------  -----------------------------------------------  ----------  
TIMING-18  Warning   Missing input or output delay                    32          
XDCC-5     Warning   User Non-Timing constraint/property overwritten  4           
RTGT-1     Advisory  RAM retargeting possibility                      4           

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (0)
6. checking no_output_delay (18)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (32)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (0)
------------------------------
 There are 0 input ports with no input delay specified.

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (18)
--------------------------------
 There are 18 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (32)
-------------------------------------
 There are 32 input ports with partial input delay specified. (HIGH)


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.077        0.000                      0                40877        0.018        0.000                      0                40861        1.914        0.000                       0                 14543  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                      Waveform(ns)         Period(ns)      Frequency(MHz)
-----                      ------------         ----------      --------------
adc_clk_p_i                {0.000 4.069}        8.138           122.880         
  clk_out1_system_pll_0_0  {0.000 4.069}        8.138           122.880         
  clk_out2_system_pll_0_0  {1.780 3.815}        4.069           245.761         
  clk_out3_system_pll_0_0  {2.289 4.323}        4.069           245.761         
  clkfbout_system_pll_0_0  {0.000 4.069}        8.138           122.880         
clk_fpga_0                 {0.000 10.000}       20.000          50.000          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
adc_clk_p_i                                                                                                                                                                  2.069        0.000                       0                     1  
  clk_out1_system_pll_0_0        0.077        0.000                      0                40861        0.018        0.000                      0                40861        2.819        0.000                       0                 14533  
  clk_out2_system_pll_0_0                                                                                                                                                    1.914        0.000                       0                     3  
  clk_out3_system_pll_0_0                                                                                                                                                    1.914        0.000                       0                     3  
  clkfbout_system_pll_0_0                                                                                                                                                    5.983        0.000                       0                     3  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock               To Clock                     WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------               --------                     -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
adc_clk_p_i              clk_out1_system_pll_0_0        3.389        0.000                      0                   16                                                                        


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock    
----------    ----------    --------    


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group               From Clock               To Clock               
----------               ----------               --------               
(none)                   clk_out1_system_pll_0_0                           
(none)                   clk_out2_system_pll_0_0                           
(none)                   clk_out3_system_pll_0_0                           
(none)                   clkfbout_system_pll_0_0                           


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  adc_clk_p_i
  To Clock:  adc_clk_p_i

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        2.069ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         adc_clk_p_i
Waveform(ns):       { 0.000 4.069 }
Period(ns):         8.138
Sources:            { adc_clk_p_i }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     PLLE2_ADV/CLKIN1  n/a            1.249         8.138       6.889      PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKIN1
Max Period        n/a     PLLE2_ADV/CLKIN1  n/a            52.633        8.138       44.495     PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1  n/a            2.000         4.069       2.069      PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKIN1
Low Pulse Width   Fast    PLLE2_ADV/CLKIN1  n/a            2.000         4.069       2.069      PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1  n/a            2.000         4.069       2.069      PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKIN1
High Pulse Width  Fast    PLLE2_ADV/CLKIN1  n/a            2.000         4.069       2.069      PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_system_pll_0_0
  To Clock:  clk_out1_system_pll_0_0

Setup :            0  Failing Endpoints,  Worst Slack        0.077ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.018ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.819ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.077ns  (required time - arrival time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[9].i_madd/i_addsub_mult_add/g_dsp48.g_dsp48e1.i_dsp48e1/CEC
                            (rising edge-triggered cell DSP48E1 clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        7.455ns  (logic 0.419ns (5.621%)  route 7.036ns (94.379%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.403ns = ( 5.735 - 8.138 ) 
    Source Clock Delay      (SCD):    -2.998ns
    Clock Pessimism Removal (CPR):    -0.542ns
  Clock Uncertainty:      0.070ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.951     0.951 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.306     2.257    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.929    -6.672 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.883    -4.789    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    -4.688 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.690    -2.998    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/aclk
    SLICE_X29Y82         FDSE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y82         FDSE (Prop_fdse_C_Q)         0.419    -2.579 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/Q
                         net (fo=5557, routed)        7.036     4.457    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[9].i_madd/i_addsub_mult_add/not_full
    DSP48_X2Y49          DSP48E1                                      r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[9].i_madd/i_addsub_mult_add/g_dsp48.g_dsp48e1.i_dsp48e1/CEC
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.729     5.735    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[9].i_madd/i_addsub_mult_add/aclk
    DSP48_X2Y49          DSP48E1                                      r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[9].i_madd/i_addsub_mult_add/g_dsp48.g_dsp48e1.i_dsp48e1/CLK
                         clock pessimism             -0.542     5.193    
                         clock uncertainty           -0.070     5.123    
    DSP48_X2Y49          DSP48E1 (Setup_dsp48e1_CLK_CEC)
                                                     -0.589     4.534    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[9].i_madd/i_addsub_mult_add/g_dsp48.g_dsp48e1.i_dsp48e1
  -------------------------------------------------------------------
                         required time                          4.534    
                         arrival time                          -4.457    
  -------------------------------------------------------------------
                         slack                                  0.077    

Slack (MET) :             0.081ns  (required time - arrival time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        7.609ns  (logic 0.419ns (5.507%)  route 7.190ns (94.493%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.489ns = ( 5.649 - 8.138 ) 
    Source Clock Delay      (SCD):    -2.998ns
    Clock Pessimism Removal (CPR):    -0.542ns
  Clock Uncertainty:      0.070ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.951     0.951 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.306     2.257    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.929    -6.672 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.883    -4.789    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    -4.688 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.690    -2.998    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/aclk
    SLICE_X29Y82         FDSE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y82         FDSE (Prop_fdse_C_Q)         0.419    -2.579 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/Q
                         net (fo=5557, routed)        7.190     4.611    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CE
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.642     5.649    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[0]/C
                         clock pessimism             -0.542     5.106    
                         clock uncertainty           -0.070     5.036    
    SLICE_X38Y119        FDRE (Setup_fdre_C_CE)      -0.344     4.692    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[0]
  -------------------------------------------------------------------
                         required time                          4.692    
                         arrival time                          -4.611    
  -------------------------------------------------------------------
                         slack                                  0.081    

Slack (MET) :             0.081ns  (required time - arrival time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[1]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        7.609ns  (logic 0.419ns (5.507%)  route 7.190ns (94.493%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.489ns = ( 5.649 - 8.138 ) 
    Source Clock Delay      (SCD):    -2.998ns
    Clock Pessimism Removal (CPR):    -0.542ns
  Clock Uncertainty:      0.070ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.951     0.951 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.306     2.257    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.929    -6.672 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.883    -4.789    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    -4.688 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.690    -2.998    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/aclk
    SLICE_X29Y82         FDSE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y82         FDSE (Prop_fdse_C_Q)         0.419    -2.579 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/Q
                         net (fo=5557, routed)        7.190     4.611    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CE
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.642     5.649    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[1]/C
                         clock pessimism             -0.542     5.106    
                         clock uncertainty           -0.070     5.036    
    SLICE_X38Y119        FDRE (Setup_fdre_C_CE)      -0.344     4.692    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[1]
  -------------------------------------------------------------------
                         required time                          4.692    
                         arrival time                          -4.611    
  -------------------------------------------------------------------
                         slack                                  0.081    

Slack (MET) :             0.081ns  (required time - arrival time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[2]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        7.609ns  (logic 0.419ns (5.507%)  route 7.190ns (94.493%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.489ns = ( 5.649 - 8.138 ) 
    Source Clock Delay      (SCD):    -2.998ns
    Clock Pessimism Removal (CPR):    -0.542ns
  Clock Uncertainty:      0.070ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.951     0.951 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.306     2.257    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.929    -6.672 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.883    -4.789    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    -4.688 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.690    -2.998    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/aclk
    SLICE_X29Y82         FDSE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y82         FDSE (Prop_fdse_C_Q)         0.419    -2.579 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/Q
                         net (fo=5557, routed)        7.190     4.611    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CE
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.642     5.649    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[2]/C
                         clock pessimism             -0.542     5.106    
                         clock uncertainty           -0.070     5.036    
    SLICE_X38Y119        FDRE (Setup_fdre_C_CE)      -0.344     4.692    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[2]
  -------------------------------------------------------------------
                         required time                          4.692    
                         arrival time                          -4.611    
  -------------------------------------------------------------------
                         slack                                  0.081    

Slack (MET) :             0.081ns  (required time - arrival time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[3]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        7.609ns  (logic 0.419ns (5.507%)  route 7.190ns (94.493%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.489ns = ( 5.649 - 8.138 ) 
    Source Clock Delay      (SCD):    -2.998ns
    Clock Pessimism Removal (CPR):    -0.542ns
  Clock Uncertainty:      0.070ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.951     0.951 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.306     2.257    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.929    -6.672 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.883    -4.789    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    -4.688 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.690    -2.998    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/aclk
    SLICE_X29Y82         FDSE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y82         FDSE (Prop_fdse_C_Q)         0.419    -2.579 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/Q
                         net (fo=5557, routed)        7.190     4.611    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CE
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.642     5.649    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[3]/C
                         clock pessimism             -0.542     5.106    
                         clock uncertainty           -0.070     5.036    
    SLICE_X38Y119        FDRE (Setup_fdre_C_CE)      -0.344     4.692    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[3]
  -------------------------------------------------------------------
                         required time                          4.692    
                         arrival time                          -4.611    
  -------------------------------------------------------------------
                         slack                                  0.081    

Slack (MET) :             0.081ns  (required time - arrival time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[4]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        7.609ns  (logic 0.419ns (5.507%)  route 7.190ns (94.493%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.489ns = ( 5.649 - 8.138 ) 
    Source Clock Delay      (SCD):    -2.998ns
    Clock Pessimism Removal (CPR):    -0.542ns
  Clock Uncertainty:      0.070ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.951     0.951 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.306     2.257    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.929    -6.672 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.883    -4.789    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    -4.688 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.690    -2.998    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/aclk
    SLICE_X29Y82         FDSE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y82         FDSE (Prop_fdse_C_Q)         0.419    -2.579 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/Q
                         net (fo=5557, routed)        7.190     4.611    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CE
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.642     5.649    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[4]/C
                         clock pessimism             -0.542     5.106    
                         clock uncertainty           -0.070     5.036    
    SLICE_X38Y119        FDRE (Setup_fdre_C_CE)      -0.344     4.692    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[4]
  -------------------------------------------------------------------
                         required time                          4.692    
                         arrival time                          -4.611    
  -------------------------------------------------------------------
                         slack                                  0.081    

Slack (MET) :             0.081ns  (required time - arrival time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[5]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        7.609ns  (logic 0.419ns (5.507%)  route 7.190ns (94.493%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.489ns = ( 5.649 - 8.138 ) 
    Source Clock Delay      (SCD):    -2.998ns
    Clock Pessimism Removal (CPR):    -0.542ns
  Clock Uncertainty:      0.070ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.951     0.951 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.306     2.257    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.929    -6.672 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.883    -4.789    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    -4.688 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.690    -2.998    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/aclk
    SLICE_X29Y82         FDSE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y82         FDSE (Prop_fdse_C_Q)         0.419    -2.579 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/Q
                         net (fo=5557, routed)        7.190     4.611    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CE
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.642     5.649    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[5]/C
                         clock pessimism             -0.542     5.106    
                         clock uncertainty           -0.070     5.036    
    SLICE_X38Y119        FDRE (Setup_fdre_C_CE)      -0.344     4.692    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[5]
  -------------------------------------------------------------------
                         required time                          4.692    
                         arrival time                          -4.611    
  -------------------------------------------------------------------
                         slack                                  0.081    

Slack (MET) :             0.081ns  (required time - arrival time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[6]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        7.609ns  (logic 0.419ns (5.507%)  route 7.190ns (94.493%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.489ns = ( 5.649 - 8.138 ) 
    Source Clock Delay      (SCD):    -2.998ns
    Clock Pessimism Removal (CPR):    -0.542ns
  Clock Uncertainty:      0.070ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.951     0.951 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.306     2.257    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.929    -6.672 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.883    -4.789    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    -4.688 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.690    -2.998    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/aclk
    SLICE_X29Y82         FDSE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y82         FDSE (Prop_fdse_C_Q)         0.419    -2.579 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/Q
                         net (fo=5557, routed)        7.190     4.611    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CE
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.642     5.649    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[6]/C
                         clock pessimism             -0.542     5.106    
                         clock uncertainty           -0.070     5.036    
    SLICE_X38Y119        FDRE (Setup_fdre_C_CE)      -0.344     4.692    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[6]
  -------------------------------------------------------------------
                         required time                          4.692    
                         arrival time                          -4.611    
  -------------------------------------------------------------------
                         slack                                  0.081    

Slack (MET) :             0.081ns  (required time - arrival time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[7]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        7.609ns  (logic 0.419ns (5.507%)  route 7.190ns (94.493%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.489ns = ( 5.649 - 8.138 ) 
    Source Clock Delay      (SCD):    -2.998ns
    Clock Pessimism Removal (CPR):    -0.542ns
  Clock Uncertainty:      0.070ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.951     0.951 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.306     2.257    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.929    -6.672 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.883    -4.789    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    -4.688 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.690    -2.998    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/aclk
    SLICE_X29Y82         FDSE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y82         FDSE (Prop_fdse_C_Q)         0.419    -2.579 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/Q
                         net (fo=5557, routed)        7.190     4.611    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CE
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.642     5.649    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X38Y119        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[7]/C
                         clock pessimism             -0.542     5.106    
                         clock uncertainty           -0.070     5.036    
    SLICE_X38Y119        FDRE (Setup_fdre_C_CE)      -0.344     4.692    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[15].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.d_out_reg[7]
  -------------------------------------------------------------------
                         required time                          4.692    
                         arrival time                          -4.611    
  -------------------------------------------------------------------
                         slack                                  0.081    

Slack (MET) :             0.083ns  (required time - arrival time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[14].i_madd/i_addsub_mult_add/g_dsp48.g_preadd.i_preadd/gen_adders[11].i_reg/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        7.571ns  (logic 0.419ns (5.534%)  route 7.152ns (94.466%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.489ns = ( 5.649 - 8.138 ) 
    Source Clock Delay      (SCD):    -2.998ns
    Clock Pessimism Removal (CPR):    -0.542ns
  Clock Uncertainty:      0.070ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.951     0.951 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.306     2.257    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.929    -6.672 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.883    -4.789    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    -4.688 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.690    -2.998    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/aclk
    SLICE_X29Y82         FDSE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y82         FDSE (Prop_fdse_C_Q)         0.419    -2.579 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/not_full_1_reg/Q
                         net (fo=5557, routed)        7.152     4.574    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[14].i_madd/i_addsub_mult_add/g_dsp48.g_preadd.i_preadd/not_full
    SLICE_X35Y121        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[14].i_madd/i_addsub_mult_add/g_dsp48.g_preadd.i_preadd/gen_adders[11].i_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.642     5.649    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[14].i_madd/i_addsub_mult_add/g_dsp48.g_preadd.i_preadd/aclk
    SLICE_X35Y121        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[14].i_madd/i_addsub_mult_add/g_dsp48.g_preadd.i_preadd/gen_adders[11].i_reg/C
                         clock pessimism             -0.542     5.106    
                         clock uncertainty           -0.070     5.036    
    SLICE_X35Y121        FDRE (Setup_fdre_C_CE)      -0.380     4.656    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_madd_array_and_accum.g_madd[14].i_madd/i_addsub_mult_add/g_dsp48.g_preadd.i_preadd/gen_adders[11].i_reg
  -------------------------------------------------------------------
                         required time                          4.656    
                         arrival time                          -4.574    
  -------------------------------------------------------------------
                         slack                                  0.083    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.018ns  (arrival time - required time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_op_paths[1].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1/A[2]
                            (rising edge-triggered cell DSP48E1 clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_system_pll_0_0 rise@0.000ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        0.437ns  (logic 0.126ns (28.863%)  route 0.311ns (71.137%))
  Logic Levels:           0  
  Clock Path Skew:        0.352ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.171ns
    Source Clock Delay      (SCD):    -0.331ns
    Clock Pessimism Removal (CPR):    -0.192ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.370     0.370 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.440     0.810    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.407    -1.596 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.544    -1.052    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.026 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.695    -0.331    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/aclk
    DSP48_X3Y38          DSP48E1                                      r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X3Y38          DSP48E1 (Prop_dsp48e1_CLK_P[36])
                                                      0.126    -0.205 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1/P[36]
                         net (fo=2, routed)           0.311     0.105    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_op_paths[1].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/P[20]
    DSP48_X3Y40          DSP48E1                                      r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_op_paths[1].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1/A[2]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     0.401 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     0.882    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727    -1.845 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592    -1.253    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.224 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.053    -0.171    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_op_paths[1].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/aclk
    DSP48_X3Y40          DSP48E1                                      r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_op_paths[1].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1/CLK
                         clock pessimism              0.192     0.021    
    DSP48_X3Y40          DSP48E1 (Hold_dsp48e1_CLK_A[2])
                                                      0.066     0.087    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_op_paths[1].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1
  -------------------------------------------------------------------
                         required time                         -0.087    
                         arrival time                           0.105    
  -------------------------------------------------------------------
                         slack                                  0.018    

Slack (MET) :             0.024ns  (arrival time - required time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][1]_srl8/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_system_pll_0_0 rise@0.000ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        0.316ns  (logic 0.141ns (44.664%)  route 0.175ns (55.336%))
  Logic Levels:           0  
  Clock Path Skew:        0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.376ns
    Source Clock Delay      (SCD):    -0.366ns
    Clock Pessimism Removal (CPR):    -0.192ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.370     0.370 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.440     0.810    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.407    -1.596 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.544    -1.052    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.026 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.660    -0.366    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/aclk
    SLICE_X59Y100        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y100        FDRE (Prop_fdre_C_Q)         0.141    -0.225 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][1]/Q
                         net (fo=1, routed)           0.175    -0.051    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/DATA_IN[1]
    SLICE_X58Y99         SRL16E                                       r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][1]_srl8/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     0.401 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     0.882    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727    -1.845 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592    -1.253    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.224 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.848    -0.376    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X58Y99         SRL16E                                       r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][1]_srl8/CLK
                         clock pessimism              0.192    -0.183    
    SLICE_X58Y99         SRL16E (Hold_srl16e_CLK_D)
                                                      0.109    -0.074    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][1]_srl8
  -------------------------------------------------------------------
                         required time                          0.074    
                         arrival time                          -0.051    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][0]_srl8/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_system_pll_0_0 rise@0.000ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        0.314ns  (logic 0.141ns (44.852%)  route 0.173ns (55.148%))
  Logic Levels:           0  
  Clock Path Skew:        0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.376ns
    Source Clock Delay      (SCD):    -0.366ns
    Clock Pessimism Removal (CPR):    -0.192ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.370     0.370 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.440     0.810    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.407    -1.596 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.544    -1.052    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.026 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.660    -0.366    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/aclk
    SLICE_X59Y100        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y100        FDRE (Prop_fdre_C_Q)         0.141    -0.225 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][0]/Q
                         net (fo=1, routed)           0.173    -0.052    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/DATA_IN[0]
    SLICE_X58Y99         SRL16E                                       r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][0]_srl8/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     0.401 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     0.882    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727    -1.845 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592    -1.253    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.224 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.848    -0.376    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X58Y99         SRL16E                                       r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][0]_srl8/CLK
                         clock pessimism              0.192    -0.183    
    SLICE_X58Y99         SRL16E (Hold_srl16e_CLK_D)
                                                      0.102    -0.081    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][0]_srl8
  -------------------------------------------------------------------
                         required time                          0.081    
                         arrival time                          -0.052    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][0]_srl8/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_system_pll_0_0 rise@0.000ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        0.314ns  (logic 0.141ns (44.852%)  route 0.173ns (55.148%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.371ns
    Source Clock Delay      (SCD):    -0.360ns
    Clock Pessimism Removal (CPR):    -0.192ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.370     0.370 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.440     0.810    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.407    -1.596 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.544    -1.052    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.026 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.666    -0.360    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/aclk
    SLICE_X83Y100        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y100        FDRE (Prop_fdre_C_Q)         0.141    -0.219 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][0]/Q
                         net (fo=1, routed)           0.173    -0.046    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/DATA_IN[0]
    SLICE_X82Y99         SRL16E                                       r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][0]_srl8/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     0.401 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     0.882    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727    -1.845 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592    -1.253    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.224 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.853    -0.371    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X82Y99         SRL16E                                       r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][0]_srl8/CLK
                         clock pessimism              0.192    -0.178    
    SLICE_X82Y99         SRL16E (Hold_srl16e_CLK_D)
                                                      0.102    -0.076    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[2].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][0]_srl8
  -------------------------------------------------------------------
                         required time                          0.076    
                         arrival time                          -0.046    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][10]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_system_pll_0_0 rise@0.000ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        0.257ns  (logic 0.141ns (54.769%)  route 0.116ns (45.231%))
  Logic Levels:           0  
  Clock Path Skew:        0.181ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.399ns
    Source Clock Delay      (SCD):    -0.387ns
    Clock Pessimism Removal (CPR):    -0.192ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.370     0.370 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.440     0.810    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.407    -1.596 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.544    -1.052    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.026 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.639    -0.387    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/aclk
    SLICE_X44Y100        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y100        FDRE (Prop_fdre_C_Q)         0.141    -0.246 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][10]/Q
                         net (fo=1, routed)           0.116    -0.130    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg_n_0_[0][10]
    SLICE_X45Y99         FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     0.401 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     0.882    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727    -1.845 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592    -1.253    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.224 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.825    -0.399    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/aclk
    SLICE_X45Y99         FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][10]/C
                         clock pessimism              0.192    -0.206    
    SLICE_X45Y99         FDRE (Hold_fdre_C_D)         0.046    -0.160    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][10]
  -------------------------------------------------------------------
                         required time                          0.160    
                         arrival time                          -0.130    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][9]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_system_pll_0_0 rise@0.000ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        0.289ns  (logic 0.141ns (48.756%)  route 0.148ns (51.244%))
  Logic Levels:           0  
  Clock Path Skew:        0.181ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.399ns
    Source Clock Delay      (SCD):    -0.387ns
    Clock Pessimism Removal (CPR):    -0.192ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.370     0.370 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.440     0.810    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.407    -1.596 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.544    -1.052    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.026 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.639    -0.387    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/aclk
    SLICE_X44Y100        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y100        FDRE (Prop_fdre_C_Q)         0.141    -0.246 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][9]/Q
                         net (fo=1, routed)           0.148    -0.098    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg_n_0_[0][9]
    SLICE_X45Y99         FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     0.401 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     0.882    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727    -1.845 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592    -1.253    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.224 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.825    -0.399    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/aclk
    SLICE_X45Y99         FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][9]/C
                         clock pessimism              0.192    -0.206    
    SLICE_X45Y99         FDRE (Hold_fdre_C_D)         0.076    -0.130    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][9]
  -------------------------------------------------------------------
                         required time                          0.130    
                         arrival time                          -0.098    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[5].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.d_out_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_system_pll_0_0 rise@0.000ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        0.321ns  (logic 0.148ns (46.151%)  route 0.173ns (53.849%))
  Logic Levels:           0  
  Clock Path Skew:        0.267ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.401ns
    Source Clock Delay      (SCD):    -0.476ns
    Clock Pessimism Removal (CPR):    -0.192ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.370     0.370 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.440     0.810    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.407    -1.596 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.544    -1.052    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.026 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.551    -0.476    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[5].i_mem/g_individual.i_mem_a/CLK
    SLICE_X50Y92         FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[5].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.d_out_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y92         FDRE (Prop_fdre_C_Q)         0.148    -0.328 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_mem_array[5].i_mem/g_individual.i_mem_a/gen_srl16.gen_mem.d_out_reg[12]/Q
                         net (fo=3, routed)           0.173    -0.155    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/DOUTA[12]
    SLICE_X49Y92         FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     0.401 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     0.882    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727    -1.845 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592    -1.253    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.224 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.823    -0.401    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/aclk
    SLICE_X49Y92         FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg_reg[12]/C
                         clock pessimism              0.192    -0.208    
    SLICE_X49Y92         FDRE (Hold_fdre_C_D)         0.017    -0.191    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[1].g_data_array.g_madd[5].g_data.i_data_casc_dly/g_buff.i_buff/gen_reg.d_reg_reg[12]
  -------------------------------------------------------------------
                         required time                          0.191    
                         arrival time                          -0.155    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][15]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][15]_srl8/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_system_pll_0_0 rise@0.000ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        0.255ns  (logic 0.141ns (55.281%)  route 0.114ns (44.719%))
  Logic Levels:           0  
  Clock Path Skew:        0.033ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.312ns
    Source Clock Delay      (SCD):    -0.385ns
    Clock Pessimism Removal (CPR):    0.040ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.370     0.370 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.440     0.810    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.407    -1.596 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.544    -1.052    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.026 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.641    -0.385    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/aclk
    SLICE_X33Y101        FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y101        FDRE (Prop_fdre_C_Q)         0.141    -0.244 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_data_array.g_madd[7].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][15]/Q
                         net (fo=1, routed)           0.114    -0.130    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/DATA_IN[15]
    SLICE_X34Y100        SRL16E                                       r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][15]_srl8/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     0.401 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     0.882    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727    -1.845 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592    -1.253    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.224 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.912    -0.312    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X34Y100        SRL16E                                       r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][15]_srl8/CLK
                         clock pessimism             -0.040    -0.352    
    SLICE_X34Y100        SRL16E (Hold_srl16e_CLK_D)
                                                      0.183    -0.169    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[3].g_mem_array[7].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][15]_srl8
  -------------------------------------------------------------------
                         required time                          0.169    
                         arrival time                          -0.130    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/fifo_2_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/DIBDI[25]
                            (rising edge-triggered cell RAMB36E1 clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_system_pll_0_0 rise@0.000ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        0.385ns  (logic 0.164ns (42.617%)  route 0.221ns (57.383%))
  Logic Levels:           0  
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.371ns
    Source Clock Delay      (SCD):    -0.475ns
    Clock Pessimism Removal (CPR):    0.054ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.370     0.370 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.440     0.810    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.407    -1.596 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.544    -1.052    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.026 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.552    -0.475    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/aclk
    SLICE_X32Y82         FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/fifo_2_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y82         FDRE (Prop_fdre_C_Q)         0.164    -0.311 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_m_data_chan_fifo.i_m_data_chan_fifo/fifo0/fifo_2_reg[27]/Q
                         net (fo=1, routed)           0.221    -0.090    system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[25]
    RAMB36_X2Y15         RAMB36E1                                     r  system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/DIBDI[25]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     0.401 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     0.882    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727    -1.845 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592    -1.253    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.224 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.852    -0.371    system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka
    RAMB36_X2Y15         RAMB36E1                                     r  system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK
                         clock pessimism             -0.054    -0.425    
    RAMB36_X2Y15         RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIBDI[25])
                                                      0.296    -0.129    system_i/writer_0/inst/fifo_0/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0
  -------------------------------------------------------------------
                         required time                          0.129    
                         arrival time                          -0.090    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][15]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][15]_srl8/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_system_pll_0_0 rise@0.000ns - clk_out1_system_pll_0_0 rise@0.000ns)
  Data Path Delay:        0.256ns  (logic 0.141ns (55.071%)  route 0.115ns (44.929%))
  Logic Levels:           0  
  Clock Path Skew:        0.033ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.382ns
    Source Clock Delay      (SCD):    -0.452ns
    Clock Pessimism Removal (CPR):    0.037ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.370     0.370 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.440     0.810    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.407    -1.596 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.544    -1.052    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.026 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.575    -0.452    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/aclk
    SLICE_X65Y84         FDRE                                         r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y84         FDRE (Prop_fdre_C_Q)         0.141    -0.311 r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[1].g_sym_data.g_sym_data_casc.i_data_sym_casc_dly/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][15]/Q
                         net (fo=1, routed)           0.115    -0.196    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b/DATA_IN[15]
    SLICE_X62Y84         SRL16E                                       r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][15]_srl8/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     0.401 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     0.882    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727    -1.845 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592    -1.253    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.224 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.842    -0.382    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b/CLK
    SLICE_X62Y84         SRL16E                                       r  system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][15]_srl8/CLK
                         clock pessimism             -0.037    -0.419    
    SLICE_X62Y84         SRL16E (Hold_srl16e_CLK_D)
                                                      0.183    -0.236    system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_mem_array[1].i_mem/g_individual.g_mem_b.i_mem_b/gen_srl16.gen_mem.mem_reg[7][15]_srl8
  -------------------------------------------------------------------
                         required time                          0.236    
                         arrival time                          -0.196    
  -------------------------------------------------------------------
                         slack                                  0.040    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_system_pll_0_0
Waveform(ns):       { 0.000 4.069 }
Period(ns):         8.138
Sources:            { system_i/pll_0/inst/plle2_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.576         8.138       5.562      RAMB36_X4Y20    system_i/dds_0/inst/rom_0/xpm_memory_base_inst/gen_rd_a.douta_reg_reg_0/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.576         8.138       5.562      RAMB36_X4Y20    system_i/dds_0/inst/rom_0/xpm_memory_base_inst/gen_rd_a.douta_reg_reg_0/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.138       5.562      RAMB18_X4Y42    system_i/dds_0/inst/rom_0/xpm_memory_base_inst/gen_rd_a.douta_reg_reg_1/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.138       5.562      RAMB18_X4Y42    system_i/dds_0/inst/rom_0/xpm_memory_base_inst/gen_rd_a.douta_reg_reg_1/CLKBWRCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.576         8.138       5.562      RAMB36_X4Y22    system_i/dds_2/inst/rom_0/xpm_memory_base_inst/gen_rd_a.douta_reg_reg_0/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.576         8.138       5.562      RAMB36_X4Y22    system_i/dds_2/inst/rom_0/xpm_memory_base_inst/gen_rd_a.douta_reg_reg_0/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.138       5.562      RAMB18_X4Y46    system_i/dds_2/inst/rom_0/xpm_memory_base_inst/gen_rd_a.douta_reg_reg_1/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.138       5.562      RAMB18_X4Y46    system_i/dds_2/inst/rom_0/xpm_memory_base_inst/gen_rd_a.douta_reg_reg_1/CLKBWRCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.576         8.138       5.562      RAMB36_X5Y25    system_i/dds_3/inst/rom_0/xpm_memory_base_inst/gen_rd_a.douta_reg_reg_0/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.576         8.138       5.562      RAMB36_X5Y25    system_i/dds_3/inst/rom_0/xpm_memory_base_inst/gen_rd_a.douta_reg_reg_0/CLKBWRCLK
Max Period        n/a     PLLE2_ADV/CLKOUT0   n/a            160.000       8.138       151.862    PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0/DP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0/DP/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0/SP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0/SP/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10/DP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10/DP/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10/SP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10/SP/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_11_11/DP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_11_11/DP/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0/DP/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0/DP/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0/SP/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_0_0/SP/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10/DP/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10/DP/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10/SP/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_10_10/SP/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_11_11/DP/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.069       2.819      SLICE_X50Y128   system_i/fir_0/U0/i_synth/g_polyphase_decimation.i_polyphase_decimation/g_semi_parallel_and_smac.g_paths[0].g_data_array.g_madd[17].g_wrap_buff.i_data_wrap_buff/i_phase_mem/gen_dram.ram_reg_0_7_11_11/DP/CLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_out2_system_pll_0_0
  To Clock:  clk_out2_system_pll_0_0

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.914ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out2_system_pll_0_0
Waveform(ns):       { 1.780 3.815 }
Period(ns):         4.069
Sources:            { system_i/pll_0/inst/plle2_adv_inst/CLKOUT1 }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     BUFG/I             n/a            2.155         4.069       1.914      BUFGCTRL_X0Y17  system_i/pll_0/inst/clkout2_buf/I
Min Period  n/a     ODDR/C             n/a            1.474         4.069       2.595      OLOGIC_X1Y133   system_i/dac_0/inst/ODDR_clk/C
Min Period  n/a     PLLE2_ADV/CLKOUT1  n/a            1.249         4.069       2.820      PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKOUT1
Max Period  n/a     PLLE2_ADV/CLKOUT1  n/a            160.000       4.069       155.931    PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKOUT1



---------------------------------------------------------------------------------------------------
From Clock:  clk_out3_system_pll_0_0
  To Clock:  clk_out3_system_pll_0_0

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.914ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out3_system_pll_0_0
Waveform(ns):       { 2.289 4.323 }
Period(ns):         4.069
Sources:            { system_i/pll_0/inst/plle2_adv_inst/CLKOUT2 }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     BUFG/I             n/a            2.155         4.069       1.914      BUFGCTRL_X0Y18  system_i/pll_0/inst/clkout3_buf/I
Min Period  n/a     ODDR/C             n/a            1.474         4.069       2.595      OLOGIC_X1Y134   system_i/dac_0/inst/ODDR_wrt/C
Min Period  n/a     PLLE2_ADV/CLKOUT2  n/a            1.249         4.069       2.820      PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKOUT2
Max Period  n/a     PLLE2_ADV/CLKOUT2  n/a            160.000       4.069       155.931    PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKOUT2



---------------------------------------------------------------------------------------------------
From Clock:  clkfbout_system_pll_0_0
  To Clock:  clkfbout_system_pll_0_0

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        5.983ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clkfbout_system_pll_0_0
Waveform(ns):       { 0.000 4.069 }
Period(ns):         8.138
Sources:            { system_i/pll_0/inst/plle2_adv_inst/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     BUFG/I              n/a            2.155         8.138       5.983      BUFGCTRL_X0Y19  system_i/pll_0/inst/clkf_buf/I
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         8.138       6.889      PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKFBOUT
Min Period  n/a     PLLE2_ADV/CLKFBIN   n/a            1.249         8.138       6.889      PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKFBIN
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        8.138       44.495     PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKFBIN
Max Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            160.000       8.138       151.862    PLLE2_ADV_X1Y1  system_i/pll_0/inst/plle2_adv_inst/CLKFBOUT



---------------------------------------------------------------------------------------------------
From Clock:  adc_clk_p_i
  To Clock:  clk_out1_system_pll_0_0

Setup :            0  Failing Endpoints,  Worst Slack        3.389ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.389ns  (required time - arrival time)
  Source:                 adc_dat_a_i[6]
                            (input port clocked by adc_clk_p_i  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/adc_0/inst/int_dat_a_reg_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - adc_clk_p_i rise@0.000ns)
  Data Path Delay:        1.085ns  (logic 1.085ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Input Delay:            1.000ns
  Clock Path Skew:        -2.474ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.474ns = ( 5.664 - 8.138 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.179ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.081ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock adc_clk_p_i rise edge)
                                                      0.000     0.000 r  
                         input delay                  1.000     1.000    
    W14                                               0.000     1.000 r  adc_dat_a_i[6] (IN)
                         net (fo=0)                   0.000     1.000    adc_dat_a_i[6]
    W14                  IBUF (Prop_ibuf_I_O)         1.085     2.085 r  adc_dat_a_i_IBUF[6]_inst/O
                         net (fo=1, routed)           0.000     2.085    system_i/adc_0/inst/adc_dat_a[6]
    ILOGIC_X1Y84         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.657     5.664    system_i/adc_0/inst/aclk
    ILOGIC_X1Y84         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[6]/C
                         clock pessimism              0.000     5.664    
                         clock uncertainty           -0.179     5.485    
    ILOGIC_X1Y84         FDRE (Setup_fdre_C_D)       -0.011     5.474    system_i/adc_0/inst/int_dat_a_reg_reg[6]
  -------------------------------------------------------------------
                         required time                          5.474    
                         arrival time                          -2.085    
  -------------------------------------------------------------------
                         slack                                  3.389    

Slack (MET) :             3.400ns  (required time - arrival time)
  Source:                 adc_dat_a_i[7]
                            (input port clocked by adc_clk_p_i  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/adc_0/inst/int_dat_a_reg_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - adc_clk_p_i rise@0.000ns)
  Data Path Delay:        1.074ns  (logic 1.074ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Input Delay:            1.000ns
  Clock Path Skew:        -2.474ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.474ns = ( 5.664 - 8.138 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.179ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.081ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock adc_clk_p_i rise edge)
                                                      0.000     0.000 r  
                         input delay                  1.000     1.000    
    Y14                                               0.000     1.000 r  adc_dat_a_i[7] (IN)
                         net (fo=0)                   0.000     1.000    adc_dat_a_i[7]
    Y14                  IBUF (Prop_ibuf_I_O)         1.074     2.074 r  adc_dat_a_i_IBUF[7]_inst/O
                         net (fo=1, routed)           0.000     2.074    system_i/adc_0/inst/adc_dat_a[7]
    ILOGIC_X1Y83         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.657     5.664    system_i/adc_0/inst/aclk
    ILOGIC_X1Y83         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[7]/C
                         clock pessimism              0.000     5.664    
                         clock uncertainty           -0.179     5.485    
    ILOGIC_X1Y83         FDRE (Setup_fdre_C_D)       -0.011     5.474    system_i/adc_0/inst/int_dat_a_reg_reg[7]
  -------------------------------------------------------------------
                         required time                          5.474    
                         arrival time                          -2.074    
  -------------------------------------------------------------------
                         slack                                  3.400    

Slack (MET) :             3.406ns  (required time - arrival time)
  Source:                 adc_dat_a_i[5]
                            (input port clocked by adc_clk_p_i  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/adc_0/inst/int_dat_a_reg_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - adc_clk_p_i rise@0.000ns)
  Data Path Delay:        1.064ns  (logic 1.064ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Input Delay:            1.000ns
  Clock Path Skew:        -2.478ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.478ns = ( 5.660 - 8.138 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.179ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.081ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock adc_clk_p_i rise edge)
                                                      0.000     0.000 r  
                         input delay                  1.000     1.000    
    W15                                               0.000     1.000 r  adc_dat_a_i[5] (IN)
                         net (fo=0)                   0.000     1.000    adc_dat_a_i[5]
    W15                  IBUF (Prop_ibuf_I_O)         1.064     2.064 r  adc_dat_a_i_IBUF[5]_inst/O
                         net (fo=1, routed)           0.000     2.064    system_i/adc_0/inst/adc_dat_a[5]
    ILOGIC_X1Y79         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.653     5.660    system_i/adc_0/inst/aclk
    ILOGIC_X1Y79         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[5]/C
                         clock pessimism              0.000     5.660    
                         clock uncertainty           -0.179     5.481    
    ILOGIC_X1Y79         FDRE (Setup_fdre_C_D)       -0.011     5.470    system_i/adc_0/inst/int_dat_a_reg_reg[5]
  -------------------------------------------------------------------
                         required time                          5.470    
                         arrival time                          -2.064    
  -------------------------------------------------------------------
                         slack                                  3.406    

Slack (MET) :             3.407ns  (required time - arrival time)
  Source:                 adc_dat_a_i[13]
                            (input port clocked by adc_clk_p_i  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/adc_0/inst/int_dat_a_reg_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - adc_clk_p_i rise@0.000ns)
  Data Path Delay:        1.063ns  (logic 1.063ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Input Delay:            1.000ns
  Clock Path Skew:        -2.478ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.478ns = ( 5.660 - 8.138 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.179ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.081ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock adc_clk_p_i rise edge)
                                                      0.000     0.000 r  
                         input delay                  1.000     1.000    
    V15                                               0.000     1.000 r  adc_dat_a_i[13] (IN)
                         net (fo=0)                   0.000     1.000    adc_dat_a_i[13]
    V15                  IBUF (Prop_ibuf_I_O)         1.063     2.063 r  adc_dat_a_i_IBUF[13]_inst/O
                         net (fo=1, routed)           0.000     2.063    system_i/adc_0/inst/adc_dat_a[13]
    ILOGIC_X1Y80         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.653     5.660    system_i/adc_0/inst/aclk
    ILOGIC_X1Y80         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[13]/C
                         clock pessimism              0.000     5.660    
                         clock uncertainty           -0.179     5.481    
    ILOGIC_X1Y80         FDRE (Setup_fdre_C_D)       -0.011     5.470    system_i/adc_0/inst/int_dat_a_reg_reg[13]
  -------------------------------------------------------------------
                         required time                          5.470    
                         arrival time                          -2.063    
  -------------------------------------------------------------------
                         slack                                  3.407    

Slack (MET) :             3.421ns  (required time - arrival time)
  Source:                 adc_dat_a_i[4]
                            (input port clocked by adc_clk_p_i  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/adc_0/inst/int_dat_a_reg_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - adc_clk_p_i rise@0.000ns)
  Data Path Delay:        1.054ns  (logic 1.054ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Input Delay:            1.000ns
  Clock Path Skew:        -2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.473ns = ( 5.665 - 8.138 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.179ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.081ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock adc_clk_p_i rise edge)
                                                      0.000     0.000 r  
                         input delay                  1.000     1.000    
    Y16                                               0.000     1.000 r  adc_dat_a_i[4] (IN)
                         net (fo=0)                   0.000     1.000    adc_dat_a_i[4]
    Y16                  IBUF (Prop_ibuf_I_O)         1.054     2.054 r  adc_dat_a_i_IBUF[4]_inst/O
                         net (fo=1, routed)           0.000     2.054    system_i/adc_0/inst/adc_dat_a[4]
    ILOGIC_X1Y86         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.658     5.665    system_i/adc_0/inst/aclk
    ILOGIC_X1Y86         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[4]/C
                         clock pessimism              0.000     5.665    
                         clock uncertainty           -0.179     5.486    
    ILOGIC_X1Y86         FDRE (Setup_fdre_C_D)       -0.011     5.475    system_i/adc_0/inst/int_dat_a_reg_reg[4]
  -------------------------------------------------------------------
                         required time                          5.475    
                         arrival time                          -2.054    
  -------------------------------------------------------------------
                         slack                                  3.421    

Slack (MET) :             3.423ns  (required time - arrival time)
  Source:                 adc_dat_a_i[2]
                            (input port clocked by adc_clk_p_i  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/adc_0/inst/int_dat_a_reg_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - adc_clk_p_i rise@0.000ns)
  Data Path Delay:        1.052ns  (logic 1.052ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Input Delay:            1.000ns
  Clock Path Skew:        -2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.473ns = ( 5.665 - 8.138 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.179ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.081ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock adc_clk_p_i rise edge)
                                                      0.000     0.000 r  
                         input delay                  1.000     1.000    
    Y17                                               0.000     1.000 r  adc_dat_a_i[2] (IN)
                         net (fo=0)                   0.000     1.000    adc_dat_a_i[2]
    Y17                  IBUF (Prop_ibuf_I_O)         1.052     2.052 r  adc_dat_a_i_IBUF[2]_inst/O
                         net (fo=1, routed)           0.000     2.052    system_i/adc_0/inst/adc_dat_a[2]
    ILOGIC_X1Y85         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.658     5.665    system_i/adc_0/inst/aclk
    ILOGIC_X1Y85         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[2]/C
                         clock pessimism              0.000     5.665    
                         clock uncertainty           -0.179     5.486    
    ILOGIC_X1Y85         FDRE (Setup_fdre_C_D)       -0.011     5.475    system_i/adc_0/inst/int_dat_a_reg_reg[2]
  -------------------------------------------------------------------
                         required time                          5.475    
                         arrival time                          -2.052    
  -------------------------------------------------------------------
                         slack                                  3.423    

Slack (MET) :             3.424ns  (required time - arrival time)
  Source:                 adc_dat_a_i[10]
                            (input port clocked by adc_clk_p_i  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/adc_0/inst/int_dat_a_reg_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - adc_clk_p_i rise@0.000ns)
  Data Path Delay:        1.055ns  (logic 1.055ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Input Delay:            1.000ns
  Clock Path Skew:        -2.469ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.469ns = ( 5.669 - 8.138 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.179ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.081ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock adc_clk_p_i rise edge)
                                                      0.000     0.000 r  
                         input delay                  1.000     1.000    
    V13                                               0.000     1.000 r  adc_dat_a_i[10] (IN)
                         net (fo=0)                   0.000     1.000    adc_dat_a_i[10]
    V13                  IBUF (Prop_ibuf_I_O)         1.055     2.055 r  adc_dat_a_i_IBUF[10]_inst/O
                         net (fo=1, routed)           0.000     2.055    system_i/adc_0/inst/adc_dat_a[10]
    ILOGIC_X1Y93         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.662     5.669    system_i/adc_0/inst/aclk
    ILOGIC_X1Y93         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[10]/C
                         clock pessimism              0.000     5.669    
                         clock uncertainty           -0.179     5.490    
    ILOGIC_X1Y93         FDRE (Setup_fdre_C_D)       -0.011     5.479    system_i/adc_0/inst/int_dat_a_reg_reg[10]
  -------------------------------------------------------------------
                         required time                          5.479    
                         arrival time                          -2.055    
  -------------------------------------------------------------------
                         slack                                  3.424    

Slack (MET) :             3.440ns  (required time - arrival time)
  Source:                 adc_dat_a_i[1]
                            (input port clocked by adc_clk_p_i  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/adc_0/inst/int_dat_a_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - adc_clk_p_i rise@0.000ns)
  Data Path Delay:        1.033ns  (logic 1.033ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Input Delay:            1.000ns
  Clock Path Skew:        -2.475ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.475ns = ( 5.663 - 8.138 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.179ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.081ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock adc_clk_p_i rise edge)
                                                      0.000     0.000 r  
                         input delay                  1.000     1.000    
    U17                                               0.000     1.000 r  adc_dat_a_i[1] (IN)
                         net (fo=0)                   0.000     1.000    adc_dat_a_i[1]
    U17                  IBUF (Prop_ibuf_I_O)         1.033     2.033 r  adc_dat_a_i_IBUF[1]_inst/O
                         net (fo=1, routed)           0.000     2.033    system_i/adc_0/inst/adc_dat_a[1]
    ILOGIC_X1Y81         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.656     5.663    system_i/adc_0/inst/aclk
    ILOGIC_X1Y81         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[1]/C
                         clock pessimism              0.000     5.663    
                         clock uncertainty           -0.179     5.484    
    ILOGIC_X1Y81         FDRE (Setup_fdre_C_D)       -0.011     5.473    system_i/adc_0/inst/int_dat_a_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          5.473    
                         arrival time                          -2.033    
  -------------------------------------------------------------------
                         slack                                  3.440    

Slack (MET) :             3.447ns  (required time - arrival time)
  Source:                 adc_dat_a_i[9]
                            (input port clocked by adc_clk_p_i  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/adc_0/inst/int_dat_a_reg_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - adc_clk_p_i rise@0.000ns)
  Data Path Delay:        1.031ns  (logic 1.031ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Input Delay:            1.000ns
  Clock Path Skew:        -2.469ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.469ns = ( 5.669 - 8.138 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.179ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.081ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock adc_clk_p_i rise edge)
                                                      0.000     0.000 r  
                         input delay                  1.000     1.000    
    V12                                               0.000     1.000 r  adc_dat_a_i[9] (IN)
                         net (fo=0)                   0.000     1.000    adc_dat_a_i[9]
    V12                  IBUF (Prop_ibuf_I_O)         1.031     2.031 r  adc_dat_a_i_IBUF[9]_inst/O
                         net (fo=1, routed)           0.000     2.031    system_i/adc_0/inst/adc_dat_a[9]
    ILOGIC_X1Y92         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.662     5.669    system_i/adc_0/inst/aclk
    ILOGIC_X1Y92         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[9]/C
                         clock pessimism              0.000     5.669    
                         clock uncertainty           -0.179     5.490    
    ILOGIC_X1Y92         FDRE (Setup_fdre_C_D)       -0.011     5.479    system_i/adc_0/inst/int_dat_a_reg_reg[9]
  -------------------------------------------------------------------
                         required time                          5.479    
                         arrival time                          -2.031    
  -------------------------------------------------------------------
                         slack                                  3.447    

Slack (MET) :             3.458ns  (required time - arrival time)
  Source:                 adc_dat_a_i[14]
                            (input port clocked by adc_clk_p_i  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/adc_0/inst/int_dat_a_reg_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Path Group:             clk_out1_system_pll_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.138ns  (clk_out1_system_pll_0_0 rise@8.138ns - adc_clk_p_i rise@0.000ns)
  Data Path Delay:        1.015ns  (logic 1.015ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Input Delay:            1.000ns
  Clock Path Skew:        -2.475ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.475ns = ( 5.663 - 8.138 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.179ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.081ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock adc_clk_p_i rise edge)
                                                      0.000     0.000 r  
                         input delay                  1.000     1.000    
    T16                                               0.000     1.000 r  adc_dat_a_i[14] (IN)
                         net (fo=0)                   0.000     1.000    adc_dat_a_i[14]
    T16                  IBUF (Prop_ibuf_I_O)         1.015     2.015 r  adc_dat_a_i_IBUF[14]_inst/O
                         net (fo=1, routed)           0.000     2.015    system_i/adc_0/inst/adc_dat_a[14]
    ILOGIC_X1Y82         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      8.138     8.138 r  
    U18                                               0.000     8.138 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     8.138    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     9.047 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181    10.228    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032     2.196 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720     3.916    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     4.007 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.656     5.663    system_i/adc_0/inst/aclk
    ILOGIC_X1Y82         FDRE                                         r  system_i/adc_0/inst/int_dat_a_reg_reg[14]/C
                         clock pessimism              0.000     5.663    
                         clock uncertainty           -0.179     5.484    
    ILOGIC_X1Y82         FDRE (Setup_fdre_C_D)       -0.011     5.473    system_i/adc_0/inst/int_dat_a_reg_reg[14]
  -------------------------------------------------------------------
                         required time                          5.473    
                         arrival time                          -2.015    
  -------------------------------------------------------------------
                         slack                                  3.458    





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_system_pll_0_0
  To Clock:  

Max Delay            16 Endpoints
Min Delay            16 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[1].ODDR_inst/C
                            (falling edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[1]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.840ns  (logic 1.839ns (99.946%)  route 0.001ns (0.054%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 fall edge)
                                                      4.069     4.069 f  
    U18                                               0.000     4.069 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     4.069    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.470 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.951    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727     2.224 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592     2.816    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.845 f  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.984     3.829    system_i/dac_0/inst/aclk
    OLOGIC_X1Y135        ODDR                                         f  system_i/dac_0/inst/DAC_DAT[1].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y135        ODDR (Prop_oddr_C_Q)         0.204     4.033 r  system_i/dac_0/inst/DAC_DAT[1].ODDR_inst/Q
                         net (fo=1, routed)           0.001     4.034    dac_dat_o_OBUF[1]
    M20                  OBUF (Prop_obuf_I_O)         1.635     5.669 r  dac_dat_o_OBUF[1]_inst/O
                         net (fo=0)                   0.000     5.669    dac_dat_o[1]
    M20                                                               r  dac_dat_o[1] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[0].ODDR_inst/C
                            (falling edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.831ns  (logic 1.830ns (99.945%)  route 0.001ns (0.055%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 fall edge)
                                                      4.069     4.069 f  
    U18                                               0.000     4.069 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     4.069    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.470 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.951    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727     2.224 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592     2.816    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.845 f  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.984     3.829    system_i/dac_0/inst/aclk
    OLOGIC_X1Y136        ODDR                                         f  system_i/dac_0/inst/DAC_DAT[0].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y136        ODDR (Prop_oddr_C_Q)         0.204     4.033 r  system_i/dac_0/inst/DAC_DAT[0].ODDR_inst/Q
                         net (fo=1, routed)           0.001     4.034    dac_dat_o_OBUF[0]
    M19                  OBUF (Prop_obuf_I_O)         1.626     5.660 r  dac_dat_o_OBUF[0]_inst/O
                         net (fo=0)                   0.000     5.660    dac_dat_o[0]
    M19                                                               r  dac_dat_o[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/ODDR_rst/C
                            (falling edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_rst_o
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.818ns  (logic 1.817ns (99.945%)  route 0.001ns (0.055%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 fall edge)
                                                      4.069     4.069 f  
    U18                                               0.000     4.069 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     4.069    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.470 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.951    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727     2.224 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592     2.816    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.845 f  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.986     3.831    system_i/dac_0/inst/aclk
    OLOGIC_X1Y108        ODDR                                         f  system_i/dac_0/inst/ODDR_rst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y108        ODDR (Prop_oddr_C_Q)         0.204     4.035 r  system_i/dac_0/inst/ODDR_rst/Q
                         net (fo=1, routed)           0.001     4.036    dac_rst_o_OBUF
    N15                  OBUF (Prop_obuf_I_O)         1.613     5.649 r  dac_rst_o_OBUF_inst/O
                         net (fo=0)                   0.000     5.649    dac_rst_o
    N15                                                               r  dac_rst_o (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/ODDR_sel/C
                            (falling edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_sel_o
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.816ns  (logic 1.815ns (99.945%)  route 0.001ns (0.055%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 fall edge)
                                                      4.069     4.069 f  
    U18                                               0.000     4.069 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     4.069    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.470 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.951    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727     2.224 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592     2.816    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.845 f  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.986     3.831    system_i/dac_0/inst/aclk
    OLOGIC_X1Y107        ODDR                                         f  system_i/dac_0/inst/ODDR_sel/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y107        ODDR (Prop_oddr_C_Q)         0.204     4.035 r  system_i/dac_0/inst/ODDR_sel/Q
                         net (fo=1, routed)           0.001     4.036    dac_sel_o_OBUF
    N16                  OBUF (Prop_obuf_I_O)         1.611     5.647 r  dac_sel_o_OBUF_inst/O
                         net (fo=0)                   0.000     5.647    dac_sel_o
    N16                                                               r  dac_sel_o (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[3].ODDR_inst/C
                            (falling edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[3]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.811ns  (logic 1.810ns (99.945%)  route 0.001ns (0.055%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 fall edge)
                                                      4.069     4.069 f  
    U18                                               0.000     4.069 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     4.069    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.470 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.951    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727     2.224 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592     2.816    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.845 f  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.982     3.827    system_i/dac_0/inst/aclk
    OLOGIC_X1Y131        ODDR                                         f  system_i/dac_0/inst/DAC_DAT[3].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y131        ODDR (Prop_oddr_C_Q)         0.204     4.031 r  system_i/dac_0/inst/DAC_DAT[3].ODDR_inst/Q
                         net (fo=1, routed)           0.001     4.032    dac_dat_o_OBUF[3]
    L20                  OBUF (Prop_obuf_I_O)         1.606     5.638 r  dac_dat_o_OBUF[3]_inst/O
                         net (fo=0)                   0.000     5.638    dac_dat_o[3]
    L20                                                               r  dac_dat_o[3] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[4].ODDR_inst/C
                            (falling edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[4]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.808ns  (logic 1.807ns (99.945%)  route 0.001ns (0.055%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 fall edge)
                                                      4.069     4.069 f  
    U18                                               0.000     4.069 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     4.069    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.470 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.951    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727     2.224 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592     2.816    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.845 f  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.980     3.825    system_i/dac_0/inst/aclk
    OLOGIC_X1Y130        ODDR                                         f  system_i/dac_0/inst/DAC_DAT[4].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y130        ODDR (Prop_oddr_C_Q)         0.204     4.029 r  system_i/dac_0/inst/DAC_DAT[4].ODDR_inst/Q
                         net (fo=1, routed)           0.001     4.030    dac_dat_o_OBUF[4]
    K19                  OBUF (Prop_obuf_I_O)         1.603     5.633 r  dac_dat_o_OBUF[4]_inst/O
                         net (fo=0)                   0.000     5.633    dac_dat_o[4]
    K19                                                               r  dac_dat_o[4] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[2].ODDR_inst/C
                            (falling edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[2]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.805ns  (logic 1.804ns (99.945%)  route 0.001ns (0.055%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 fall edge)
                                                      4.069     4.069 f  
    U18                                               0.000     4.069 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     4.069    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.470 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.951    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727     2.224 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592     2.816    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.845 f  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.982     3.827    system_i/dac_0/inst/aclk
    OLOGIC_X1Y132        ODDR                                         f  system_i/dac_0/inst/DAC_DAT[2].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y132        ODDR (Prop_oddr_C_Q)         0.204     4.031 r  system_i/dac_0/inst/DAC_DAT[2].ODDR_inst/Q
                         net (fo=1, routed)           0.001     4.032    dac_dat_o_OBUF[2]
    L19                  OBUF (Prop_obuf_I_O)         1.600     5.633 r  dac_dat_o_OBUF[2]_inst/O
                         net (fo=0)                   0.000     5.633    dac_dat_o[2]
    L19                                                               r  dac_dat_o[2] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[5].ODDR_inst/C
                            (falling edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[5]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.807ns  (logic 1.806ns (99.945%)  route 0.001ns (0.055%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 fall edge)
                                                      4.069     4.069 f  
    U18                                               0.000     4.069 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     4.069    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.470 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.951    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727     2.224 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592     2.816    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.845 f  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.980     3.825    system_i/dac_0/inst/aclk
    OLOGIC_X1Y129        ODDR                                         f  system_i/dac_0/inst/DAC_DAT[5].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y129        ODDR (Prop_oddr_C_Q)         0.204     4.029 r  system_i/dac_0/inst/DAC_DAT[5].ODDR_inst/Q
                         net (fo=1, routed)           0.001     4.030    dac_dat_o_OBUF[5]
    J19                  OBUF (Prop_obuf_I_O)         1.602     5.632 r  dac_dat_o_OBUF[5]_inst/O
                         net (fo=0)                   0.000     5.632    dac_dat_o[5]
    J19                                                               r  dac_dat_o[5] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[6].ODDR_inst/C
                            (falling edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[6]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.770ns  (logic 1.769ns (99.943%)  route 0.001ns (0.057%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 fall edge)
                                                      4.069     4.069 f  
    U18                                               0.000     4.069 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     4.069    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.470 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.951    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727     2.224 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592     2.816    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.845 f  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.984     3.829    system_i/dac_0/inst/aclk
    OLOGIC_X1Y116        ODDR                                         f  system_i/dac_0/inst/DAC_DAT[6].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y116        ODDR (Prop_oddr_C_Q)         0.204     4.033 r  system_i/dac_0/inst/DAC_DAT[6].ODDR_inst/Q
                         net (fo=1, routed)           0.001     4.034    dac_dat_o_OBUF[6]
    J20                  OBUF (Prop_obuf_I_O)         1.565     5.599 r  dac_dat_o_OBUF[6]_inst/O
                         net (fo=0)                   0.000     5.599    dac_dat_o[6]
    J20                                                               r  dac_dat_o[6] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[7].ODDR_inst/C
                            (falling edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[7]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.767ns  (logic 1.766ns (99.943%)  route 0.001ns (0.057%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 fall edge)
                                                      4.069     4.069 f  
    U18                                               0.000     4.069 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     4.069    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.470 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.951    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.727     2.224 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.592     2.816    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.845 f  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       0.984     3.829    system_i/dac_0/inst/aclk
    OLOGIC_X1Y115        ODDR                                         f  system_i/dac_0/inst/DAC_DAT[7].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y115        ODDR (Prop_oddr_C_Q)         0.204     4.033 r  system_i/dac_0/inst/DAC_DAT[7].ODDR_inst/Q
                         net (fo=1, routed)           0.001     4.034    dac_dat_o_OBUF[7]
    H20                  OBUF (Prop_obuf_I_O)         1.562     5.596 r  dac_dat_o_OBUF[7]_inst/O
                         net (fo=0)                   0.000     5.596    dac_dat_o[7]
    H20                                                               r  dac_dat_o[7] (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[10].ODDR_inst/C
                            (rising edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[10]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.392ns  (logic 3.391ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     0.909 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.090    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032    -5.942 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720    -4.222    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -4.131 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.827    -2.304    system_i/dac_0/inst/aclk
    OLOGIC_X1Y120        ODDR                                         r  system_i/dac_0/inst/DAC_DAT[10].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y120        ODDR (Prop_oddr_C_Q)         0.411    -1.893 r  system_i/dac_0/inst/DAC_DAT[10].ODDR_inst/Q
                         net (fo=1, routed)           0.001    -1.892    dac_dat_o_OBUF[10]
    F19                  OBUF (Prop_obuf_I_O)         2.980     1.088 r  dac_dat_o_OBUF[10]_inst/O
                         net (fo=0)                   0.000     1.088    dac_dat_o[10]
    F19                                                               r  dac_dat_o[10] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[8].ODDR_inst/C
                            (rising edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[8]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.391ns  (logic 3.390ns (99.970%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     0.909 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.090    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032    -5.942 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720    -4.222    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -4.131 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.833    -2.299    system_i/dac_0/inst/aclk
    OLOGIC_X1Y114        ODDR                                         r  system_i/dac_0/inst/DAC_DAT[8].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y114        ODDR (Prop_oddr_C_Q)         0.411    -1.888 r  system_i/dac_0/inst/DAC_DAT[8].ODDR_inst/Q
                         net (fo=1, routed)           0.001    -1.887    dac_dat_o_OBUF[8]
    G19                  OBUF (Prop_obuf_I_O)         2.979     1.092 r  dac_dat_o_OBUF[8]_inst/O
                         net (fo=0)                   0.000     1.092    dac_dat_o[8]
    G19                                                               r  dac_dat_o[8] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[9].ODDR_inst/C
                            (rising edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[9]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.391ns  (logic 3.390ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     0.909 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.090    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032    -5.942 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720    -4.222    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -4.131 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.833    -2.299    system_i/dac_0/inst/aclk
    OLOGIC_X1Y113        ODDR                                         r  system_i/dac_0/inst/DAC_DAT[9].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y113        ODDR (Prop_oddr_C_Q)         0.411    -1.888 r  system_i/dac_0/inst/DAC_DAT[9].ODDR_inst/Q
                         net (fo=1, routed)           0.001    -1.887    dac_dat_o_OBUF[9]
    G20                  OBUF (Prop_obuf_I_O)         2.979     1.092 r  dac_dat_o_OBUF[9]_inst/O
                         net (fo=0)                   0.000     1.092    dac_dat_o[9]
    G20                                                               r  dac_dat_o[9] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[11].ODDR_inst/C
                            (rising edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[11]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.397ns  (logic 3.396ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     0.909 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.090    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032    -5.942 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720    -4.222    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -4.131 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.827    -2.304    system_i/dac_0/inst/aclk
    OLOGIC_X1Y119        ODDR                                         r  system_i/dac_0/inst/DAC_DAT[11].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y119        ODDR (Prop_oddr_C_Q)         0.411    -1.893 r  system_i/dac_0/inst/DAC_DAT[11].ODDR_inst/Q
                         net (fo=1, routed)           0.001    -1.892    dac_dat_o_OBUF[11]
    F20                  OBUF (Prop_obuf_I_O)         2.985     1.093 r  dac_dat_o_OBUF[11]_inst/O
                         net (fo=0)                   0.000     1.093    dac_dat_o[11]
    F20                                                               r  dac_dat_o[11] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[13].ODDR_inst/C
                            (rising edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[13]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.402ns  (logic 3.401ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     0.909 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.090    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032    -5.942 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720    -4.222    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -4.131 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.837    -2.295    system_i/dac_0/inst/aclk
    OLOGIC_X1Y142        ODDR                                         r  system_i/dac_0/inst/DAC_DAT[13].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y142        ODDR (Prop_oddr_C_Q)         0.411    -1.884 r  system_i/dac_0/inst/DAC_DAT[13].ODDR_inst/Q
                         net (fo=1, routed)           0.001    -1.883    dac_dat_o_OBUF[13]
    D19                  OBUF (Prop_obuf_I_O)         2.990     1.107 r  dac_dat_o_OBUF[13]_inst/O
                         net (fo=0)                   0.000     1.107    dac_dat_o[13]
    D19                                                               r  dac_dat_o[13] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[12].ODDR_inst/C
                            (rising edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[12]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.403ns  (logic 3.402ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     0.909 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.090    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032    -5.942 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720    -4.222    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -4.131 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.837    -2.295    system_i/dac_0/inst/aclk
    OLOGIC_X1Y141        ODDR                                         r  system_i/dac_0/inst/DAC_DAT[12].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y141        ODDR (Prop_oddr_C_Q)         0.411    -1.884 r  system_i/dac_0/inst/DAC_DAT[12].ODDR_inst/Q
                         net (fo=1, routed)           0.001    -1.883    dac_dat_o_OBUF[12]
    D20                  OBUF (Prop_obuf_I_O)         2.991     1.108 r  dac_dat_o_OBUF[12]_inst/O
                         net (fo=0)                   0.000     1.108    dac_dat_o[12]
    D20                                                               r  dac_dat_o[12] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[7].ODDR_inst/C
                            (rising edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[7]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.408ns  (logic 3.407ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     0.909 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.090    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032    -5.942 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720    -4.222    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -4.131 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.832    -2.300    system_i/dac_0/inst/aclk
    OLOGIC_X1Y115        ODDR                                         r  system_i/dac_0/inst/DAC_DAT[7].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y115        ODDR (Prop_oddr_C_Q)         0.411    -1.889 r  system_i/dac_0/inst/DAC_DAT[7].ODDR_inst/Q
                         net (fo=1, routed)           0.001    -1.888    dac_dat_o_OBUF[7]
    H20                  OBUF (Prop_obuf_I_O)         2.996     1.108 r  dac_dat_o_OBUF[7]_inst/O
                         net (fo=0)                   0.000     1.108    dac_dat_o[7]
    H20                                                               r  dac_dat_o[7] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[6].ODDR_inst/C
                            (rising edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[6]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.410ns  (logic 3.409ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     0.909 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.090    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032    -5.942 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720    -4.222    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -4.131 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.832    -2.300    system_i/dac_0/inst/aclk
    OLOGIC_X1Y116        ODDR                                         r  system_i/dac_0/inst/DAC_DAT[6].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y116        ODDR (Prop_oddr_C_Q)         0.411    -1.889 r  system_i/dac_0/inst/DAC_DAT[6].ODDR_inst/Q
                         net (fo=1, routed)           0.001    -1.888    dac_dat_o_OBUF[6]
    J20                  OBUF (Prop_obuf_I_O)         2.998     1.111 r  dac_dat_o_OBUF[6]_inst/O
                         net (fo=0)                   0.000     1.111    dac_dat_o[6]
    J20                                                               r  dac_dat_o[6] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[5].ODDR_inst/C
                            (rising edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[5]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.448ns  (logic 3.447ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     0.909 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.090    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032    -5.942 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720    -4.222    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -4.131 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.827    -2.304    system_i/dac_0/inst/aclk
    OLOGIC_X1Y129        ODDR                                         r  system_i/dac_0/inst/DAC_DAT[5].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y129        ODDR (Prop_oddr_C_Q)         0.411    -1.893 r  system_i/dac_0/inst/DAC_DAT[5].ODDR_inst/Q
                         net (fo=1, routed)           0.001    -1.892    dac_dat_o_OBUF[5]
    J19                  OBUF (Prop_obuf_I_O)         3.036     1.144 r  dac_dat_o_OBUF[5]_inst/O
                         net (fo=0)                   0.000     1.144    dac_dat_o[5]
    J19                                                               r  dac_dat_o[5] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 system_i/dac_0/inst/DAC_DAT[4].ODDR_inst/C
                            (rising edge-triggered cell ODDR clocked by clk_out1_system_pll_0_0  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            dac_dat_o[4]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.448ns  (logic 3.447ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.164ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.121ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     0.909 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.090    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.032    -5.942 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.720    -4.222    system_i/pll_0/inst/clk_out1_system_pll_0_0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -4.131 r  system_i/pll_0/inst/clkout1_buf/O
                         net (fo=14533, routed)       1.827    -2.304    system_i/dac_0/inst/aclk
    OLOGIC_X1Y130        ODDR                                         r  system_i/dac_0/inst/DAC_DAT[4].ODDR_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y130        ODDR (Prop_oddr_C_Q)         0.411    -1.893 r  system_i/dac_0/inst/DAC_DAT[4].ODDR_inst/Q
                         net (fo=1, routed)           0.001    -1.892    dac_dat_o_OBUF[4]
    K19                  OBUF (Prop_obuf_I_O)         3.036     1.145 r  dac_dat_o_OBUF[4]_inst/O
                         net (fo=0)                   0.000     1.145    dac_dat_o[4]
    K19                                                               r  dac_dat_o[4] (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out2_system_pll_0_0
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 system_i/dac_0/inst/ODDR_clk/C
                            (falling edge-triggered cell ODDR clocked by clk_out2_system_pll_0_0  {rise@1.780ns fall@3.815ns period=4.069ns})
  Destination:            dac_clk_o
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.842ns  (logic 1.841ns (99.946%)  route 0.001ns (0.054%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.157ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.106ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_system_pll_0_0 fall edge)
                                                      3.815     3.815 f  
    U18                                               0.000     3.815 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     3.815    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.216 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.697    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                     -2.727     1.970 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.592     2.562    system_i/pll_0/inst/clk_out2_system_pll_0_0
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     2.591 f  system_i/pll_0/inst/clkout2_buf/O
                         net (fo=1, routed)           0.984     3.575    system_i/dac_0/inst/ddr_clk
    OLOGIC_X1Y133        ODDR                                         f  system_i/dac_0/inst/ODDR_clk/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y133        ODDR (Prop_oddr_C_Q)         0.204     3.779 r  system_i/dac_0/inst/ODDR_clk/Q
                         net (fo=1, routed)           0.001     3.780    dac_clk_o_OBUF
    M18                  OBUF (Prop_obuf_I_O)         1.637     5.417 r  dac_clk_o_OBUF_inst/O
                         net (fo=0)                   0.000     5.417    dac_clk_o
    M18                                                               r  dac_clk_o (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 system_i/dac_0/inst/ODDR_clk/C
                            (rising edge-triggered cell ODDR clocked by clk_out2_system_pll_0_0  {rise@1.780ns fall@3.815ns period=4.069ns})
  Destination:            dac_clk_o
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.482ns  (logic 3.481ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.157ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.106ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_system_pll_0_0 rise edge)
                                                      1.780     1.780 r  
    U18                                               0.000     1.780 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     1.780    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     2.689 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     3.870    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                     -8.032    -4.162 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.720    -2.442    system_i/pll_0/inst/clk_out2_system_pll_0_0
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.091    -2.351 r  system_i/pll_0/inst/clkout2_buf/O
                         net (fo=1, routed)           1.832    -0.519    system_i/dac_0/inst/ddr_clk
    OLOGIC_X1Y133        ODDR                                         r  system_i/dac_0/inst/ODDR_clk/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y133        ODDR (Prop_oddr_C_Q)         0.411    -0.108 r  system_i/dac_0/inst/ODDR_clk/Q
                         net (fo=1, routed)           0.001    -0.107    dac_clk_o_OBUF
    M18                  OBUF (Prop_obuf_I_O)         3.070     2.962 r  dac_clk_o_OBUF_inst/O
                         net (fo=0)                   0.000     2.962    dac_clk_o
    M18                                                               r  dac_clk_o (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out3_system_pll_0_0
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 system_i/dac_0/inst/ODDR_wrt/C
                            (rising edge-triggered cell ODDR clocked by clk_out3_system_pll_0_0  {rise@2.289ns fall@4.323ns period=4.069ns})
  Destination:            dac_wrt_o
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.855ns  (logic 1.854ns (99.946%)  route 0.001ns (0.054%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.157ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.106ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out3_system_pll_0_0 rise edge)
                                                      2.289     2.289 r  
    U18                                               0.000     2.289 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     2.289    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     2.690 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     3.171    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
                                                     -2.727     0.444 r  system_i/pll_0/inst/plle2_adv_inst/CLKOUT2
                         net (fo=1, routed)           0.592     1.036    system_i/pll_0/inst/clk_out3_system_pll_0_0
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     1.065 r  system_i/pll_0/inst/clkout3_buf/O
                         net (fo=1, routed)           0.984     2.049    system_i/dac_0/inst/wrt_clk
    OLOGIC_X1Y134        ODDR                                         r  system_i/dac_0/inst/ODDR_wrt/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y134        ODDR (Prop_oddr_C_Q)         0.204     2.253 r  system_i/dac_0/inst/ODDR_wrt/Q
                         net (fo=1, routed)           0.001     2.254    dac_wrt_o_OBUF
    M17                  OBUF (Prop_obuf_I_O)         1.650     3.904 r  dac_wrt_o_OBUF_inst/O
                         net (fo=0)                   0.000     3.904    dac_wrt_o
    M17                                                               r  dac_wrt_o (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 system_i/dac_0/inst/ODDR_wrt/C
                            (falling edge-triggered cell ODDR clocked by clk_out3_system_pll_0_0  {rise@2.289ns fall@4.323ns period=4.069ns})
  Destination:            dac_wrt_o
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.495ns  (logic 3.494ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.157ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.106ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out3_system_pll_0_0 fall edge)
                                                      0.254     0.254 f  
    U18                                               0.000     0.254 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.254    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     1.163 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.344    system_i/pll_0/inst/clk_in1_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
                                                     -8.032    -5.688 f  system_i/pll_0/inst/plle2_adv_inst/CLKOUT2
                         net (fo=1, routed)           1.720    -3.968    system_i/pll_0/inst/clk_out3_system_pll_0_0
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.091    -3.877 f  system_i/pll_0/inst/clkout3_buf/O
                         net (fo=1, routed)           1.832    -2.045    system_i/dac_0/inst/wrt_clk
    OLOGIC_X1Y134        ODDR                                         f  system_i/dac_0/inst/ODDR_wrt/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y134        ODDR (Prop_oddr_C_Q)         0.411    -1.634 r  system_i/dac_0/inst/ODDR_wrt/Q
                         net (fo=1, routed)           0.001    -1.633    dac_wrt_o_OBUF
    M17                  OBUF (Prop_obuf_I_O)         3.083     1.449 r  dac_wrt_o_OBUF_inst/O
                         net (fo=0)                   0.000     1.449    dac_wrt_o
    M17                                                               r  dac_wrt_o (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clkfbout_system_pll_0_0
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 system_i/pll_0/inst/plle2_adv_inst/CLKFBOUT
                            (clock source 'clkfbout_system_pll_0_0'  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/pll_0/inst/plle2_adv_inst/CLKFBIN
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.485ns  (logic 0.029ns (1.953%)  route 1.456ns (98.047%))
  Logic Levels:           1  (BUFG=1)
  Clock Uncertainty:      0.146ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.082ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clkfbout_system_pll_0_0 fall edge)
                                                      4.069     4.069 f  
    U18                                               0.000     4.069 f  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     4.069    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.401     4.470 f  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           0.481     4.951    system_i/pll_0/inst/clk_in1_system_pll_0_0
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT)
                                                     -2.727     2.224 f  system_i/pll_0/inst/plle2_adv_inst/CLKFBOUT
                         net (fo=1, routed)           0.592     2.816    system_i/pll_0/inst/clkfbout_system_pll_0_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     2.845 f  system_i/pll_0/inst/clkf_buf/O
                         net (fo=1, routed)           0.864     3.709    system_i/pll_0/inst/clkfbout_buf_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV                                    f  system_i/pll_0/inst/plle2_adv_inst/CLKFBIN
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 system_i/pll_0/inst/plle2_adv_inst/CLKFBOUT
                            (clock source 'clkfbout_system_pll_0_0'  {rise@0.000ns fall@4.069ns period=8.138ns})
  Destination:            system_i/pll_0/inst/plle2_adv_inst/CLKFBIN
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.429ns  (logic 0.091ns (2.654%)  route 3.338ns (97.346%))
  Logic Levels:           1  (BUFG=1)
  Clock Uncertainty:      0.146ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.082ns
    Phase Error              (PE):    0.098ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clkfbout_system_pll_0_0 rise edge)
                                                      0.000     0.000 r  
    U18                                               0.000     0.000 r  adc_clk_p_i (IN)
                         net (fo=0)                   0.000     0.000    system_i/pll_0/inst/clk_in1_p
    U18                  IBUFDS (Prop_ibufds_I_O)     0.909     0.909 r  system_i/pll_0/inst/clkin1_ibufgds/O
                         net (fo=1, routed)           1.181     2.090    system_i/pll_0/inst/clk_in1_system_pll_0_0
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT)
                                                     -8.032    -5.942 r  system_i/pll_0/inst/plle2_adv_inst/CLKFBOUT
                         net (fo=1, routed)           1.720    -4.222    system_i/pll_0/inst/clkfbout_system_pll_0_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.091    -4.131 r  system_i/pll_0/inst/clkf_buf/O
                         net (fo=1, routed)           1.618    -2.513    system_i/pll_0/inst/clkfbout_buf_system_pll_0_0
    PLLE2_ADV_X1Y1       PLLE2_ADV                                    r  system_i/pll_0/inst/plle2_adv_inst/CLKFBIN
  -------------------------------------------------------------------    -------------------





